This invention relates to a semiconductor device formed on a principal surface of a semiconductor substrate provided with a silicon/isolation film structure (hereinafter referred to as SOI), and more particularly to a layout constitution of a basic cell constituting an internal circuit of the semiconductor device.
In general, in a method for acquiring an large scale integration circuit (LSI), there is a full custom system that function and performance are taken seriously and a semicustom system that a general purpose property and a short TAT are taken seriously. The semi-custom system is such a system that a part of a component of the LSI is prepared in advance and a chip designer performs remaining designs based on a circuit design information from an LSI designer. The LSI having the desired functions is thereby achieved. This technique is used widely, since the number of manpower required in manual designs can be so reduced. Typical examples in which the technique is used are a gate array, an embedded array and a standard cell.
For both of the aforesaid systems, a library for the LSI designer of various circuit blocks and a library for the chip designer are prepared in advance based on a basic cell defining a transistor or a logic gate as a minimum unit. The LSI designer designs an aimed LSI circuit by the use of this library, and the chip designer performs the above-mentioned remaining designs based on this design information and the library for the LSI designer. Accordingly, the LSI having the desired functions is achieved. In the gate array and the embedded array, the basic cell defining the aforesaid transistor or logic gate as the minimum unit is built-in on the chip in advance. Consequently, it becomes possible to develop the LSI within the short TAT more efficiently.
In these semi-custom systems, the development of the LSI using the LSI component prepared in advance only is performed to obtain an advantageous merit in the general purpose and a development of the short TAT. However, a square measure of the chip tends to become large in some cases. Therefore, it is extremely important to reduce the square measure of the chip by reducing a square measure of the basic cell.
As a method for reducing such a square measure of the basic cell, a CMOS technology using a silicon/the isolation film structure (hereinafter referred to as a SOI.cndot.CMOS technology) is proposed. However, as will later be described more in detail, the problem is not solved sufficiently even by the proposed SOI.cndot.CMOS technology.